This article details the operation of the ripple counter.

RIPPLE COUNTER

The ripple counter is shown in figure one. It uses three JK flip flops labeled U1, U2 and U3. The J and K inputs of each flip flop are held high. The set input is not used. When the reset input is high, all QN outputs are set high.

Note that the output QN1 of U1 is connected to the clock input of U2. Likewise the output QN2 of U2 is connected to the clock input of U3.

WAVEFORM DIAGRAM

In order to follow this explanation, use the waveform diagram shown in figure two. It shows eleven time periods labeled T0 through T10. Each time period covers one clock cycle.

During the first clock cycle, the reset is high. The high reset causes the outputs QN1, QN2 and QN3 to go high. The Q outputs of the flip flops are not used.

During the second clock cycle T1, the output QN1 goes low. the outputs QN2 and QN3 remain high. The outputs QN2 and QN3 remain high because they do not have a high level at their clock inputs.

During the third clock cycle T2, the output QN1 goes high. the output QN1 is connected to the clock input of U2. Hence, when QN1 goes high, the QN2 goes low. QN3 remains high.

During the fourth clock cycle T3, the output QN1 goes low. QN2 stays low and QN3 stays high.

During the fifth clock cycle T4, the output QN1 goes high, QN2 goes high and QN3 goes low.

In the ninth clock cycle (t8), the outputs QN1, QN2 and QN3 go high again and the process is restarted.

In summary, when the clock goes high, the output QN1 changes state. When the output QN1 goes high, the output QN2 changes state. When QN2 goes high, the output QN3 changes state. The result is that QN1, QN2 and QN3 are toggling (between high and low) at different rates.

The frequency of the QN1 output is equal to half the frequency of the clock. The frequency of the QN2 output is equal to half the frequency of the QN1 output . The frequency of the QN3 output is equal to half the frequency of the QN2 output.

In figure three we see the outputs QN3, QN2 and QN1 (for each time period t0 through t8) arranged in the form “QN3 QN2 QN1.”

POSITIVE LOGIC

Positive logic is implemented by declaring the logic high state as the active state. In positive logic, we assign the active high state the binary value 1 and the inactive low state the binary value 0.

In figure four, we have “QN3 QN2 QN1” with QN3 being the most significant digit of a three digit binary number and QN1 being the least significant digit of a three digit binary number. Using positive logic, the counter counts down from 111 to 000 in binary or from 7 to 0 in decimal.

NEGATIVE LOGIC

Negative logic is implemented by declaring the low state the active state. In negative logic, we assign the low state a 1. We assign the high state a 0.

In figure 5, we have “QN3 QN2 QN1” with QN3 being the most significant digit of a three digit binary number and QN1 being the least significant digit of a three digit binary number. Using negative logic, the counter counts up from 000 to 111 in binary or from 0 to 7 in decimal.

References:

I have a Bachelor of Science in Electrical Engineering and experience as an electronics technician.

Digital Circuits and Microprocessors

Herbert Taub

ISBN 0-07-062945-5